High Bandwidth Flash title card showing an HBF stack of core dies on a logic die and interposer

What Is HBF? High Bandwidth Flash vs HBM, the Next AI Memory

Key takeaways

  • HBF stacks NAND flash like HBM stacks DRAM, trading some speed for far more capacity.
  • One HBF stack targets 512GB to 1TB, versus a 64GB maximum under the HBM4 spec.
  • Sandisk and SK hynix published the first HBF specification on Aug. 3, 2026.
High Bandwidth Flash title card showing an HBF stack of core dies on a logic die and interposer
HBF title card with a stacked die drawing. Image: Techqio

High Bandwidth Flash (HBF) stacks NAND flash the way HBM stacks DRAM, and chipmakers see it as a way past HBM’s structural limits. HBM, or high-bandwidth memory, comes up in almost every AI story: demand has grown so fast that NVIDIA GPUs sell out, and the HBM inside them has become one of the most valuable parts in the chip industry.

One HBF stack targets 512GB to 1TB, eight to 16 times the 64GB an HBM4 stack can hold, and Sandisk and SK hynix published its first specification in August 2026. That capacity is what could make large AI models cheaper to run.

Illustration of stacked NAND flash dies on a circuit board labeled HBF High Bandwidth Flash
Illustration of NAND dies stacked on a circuit board. Image: Techqio

What is High Bandwidth Flash?

When a large language model like ChatGPT answers slowly or costs a lot to run, memory capacity is often part of the reason. HBM, the main memory in today’s AI accelerators, is extremely fast, but it is expensive and holds only so much.

High Bandwidth Flash is the answer to that problem. Put simply, it piles NAND flash, the memory used for storage, into a tall vertical stack, which sharply raises speed while storing far more data than HBM. Sandisk says in its Memory-Centric AI blog post that it invented HBF to close the gap between AI models’ memory demands and DRAM’s slow progress, a gap known as the memory wall.

Diagram of HBF: NAND core dies stacked over TSVs and a logic base die
NAND core dies, TSVs and a logic base die. Image: Techqio

HBF vs HBM: what is the difference?

Picture a study. HBM is a small shelf right next to the desk, and HBF is a large bookcase filling a whole wall. You can grab a book from the desk shelf instantly, but it holds only a few. The wall bookcase takes a moment longer to reach, yet it stores far more knowledge than the shelf ever could.

Study with a small desk shelf and a wall of bookcases
A desk shelf and a wall of bookcases. Image: Techqio

The same split shows up in how AI works. Training reads and writes data constantly, so ultra-fast HBM is essential. Inference, where a trained model generates answers, depends on laying out huge amounts of data at once and referring to it, so high-capacity HBF is seen as the more efficient fit.

Structurally, the two are close cousins. Both use TSVs (through-silicon vias) to connect stacked chips vertically and sit beside the processor on a silicon interposer. The decisive difference is what goes inside: DRAM or NAND flash.

Render of chips stacked vertically with connecting pillars
Render of a chip stack joined by vertical pillars. Image: Techqio

Here is how the two compare side by side.

SpecHBM (High Bandwidth Memory)HBF (High Bandwidth Flash)
Core materialDRAM (loses data without power)NAND flash (keeps data without power)
Capacity per stackUp to 64GB under the HBM4 spec512GB to 1TB or more
Transfer speedVery high (up to 2 TB/s per HBM4 stack)High (about 1.6 TB/s target)
Main roleAI training and real-time computeAI inference and large data caching
CostVery expensiveRelatively cheaper

HBF’s biggest strength is capacity. The JEDEC HBM4 standard tops out at 64GB per stack with 16 layers of 32Gb dies, while a single HBF stack can hold 512GB and up to 1TB. HBF targets bandwidth of about 1.638 TB/s, tens of times faster than the SSDs most people use, to feed data to the GPU.

The trade-off is endurance. NAND cells wear out after about 100,000 write cycles, while DRAM has no such limit, which is one reason HBF suits read-heavy inference rather than training.

Bar chart: HBM4 maximum 64GB per stack vs HBF 512GB and 1TB
Bar chart of HBM4 and HBF capacity. Source: JEDEC HBM4 spec; HBF target capacity

How does HBF get 1.6 TB/s out of slow NAND?

NAND flash has a reputation for being slow, so how does HBF reach this kind of bandwidth? The answer is parallelism. Conventional NAND sends data through a fairly narrow path, one piece after another. HBF stacks many NAND chips vertically and pushes data through thousands of TSVs at once.

HBM cube of 16-high DRAM and HBF cube of 16-high NAND beside a GPU on an interposer
HBM and HBF stacks beside a GPU. Image: Techqio

Sandisk and SK hynix both point to the same key part: the logic base die. It works like the building manager of the NAND stack, organizing data from slow-reading NAND in advance and managing bottlenecks so the GPU is not left waiting.

Add hybrid bonding, which connects chips directly to each other, and the path data travels gets even shorter.

Diagram of hybrid bonding with copper-to-copper pads between a top chip and a bottom chip
Cu-Cu hybrid bonding between two chips. Image: Techqio

Samsung, SK hynix and Sandisk take different paths

The companies around HBF are moving quickly, and the most aggressive is SK hynix, today’s HBM leader. It announced an AI-focused NAND lineup called AIN (AI-NAND), and the bandwidth-focused AIN B line in its NAND strategy is the HBF product, built from stacked NAND dies.

The partnership with Sandisk, one of the pioneers of NAND, stands out. The two companies laid out a fairly specific roadmap of prototypes in the first half of 2026, then mass production and supply to customers such as NVIDIA in 2027. Their standards work has moved on schedule: Sandisk and SK hynix released the first HBF technical specification through the Open Compute Project on Aug. 3, 2026, six months after they started the work, and Google and Tenstorrent joined the consortium.

Diagram of an HBF NAND stack and an HBM DRAM stack on an interposer with a memory controller and GPU
HBF and HBM stacks with a memory controller and GPU. Image: Techqio

Samsung is taking a different approach. It already has its own hybrid memory technology, such as CMM-H (CXL Memory Module-Hybrid), so rather than going all in on HBF, it chose to watch the market and join the related consortium.

Samsung’s strength is turnkey production that spans memory, foundry and packaging. It is counting on V-NAND with 400 or more layers, targeted for 2026, to take the lead quickly once the market opens in earnest.

Cross-section of a vertical 3D NAND cell showing control gate, storage layer and tunnel oxide around a vertical channel
Structure of a vertical 3D NAND cell. Photo: David Gianluigi Refaldi / Wikimedia Commons (CC BY-SA 4.0)

Will HBF replace HBM?

Once HBF is commercialized, the first change people will feel is cheaper and faster AI services. Running a large model today means tying together several very expensive GPUs. With HBF, fewer GPUs could handle massive data efficiently, which lowers operating costs for companies and means faster, cheaper AI services for users.

Comparison table of HBM4 and HBF: memory type, speed, power, write cycles, 64GB vs 512GB, 2048 vs 1638 GB/s
HBM and HBF comparison table. Image: Techqio

High Bandwidth Flash will not fully replace HBM. More likely, the two will coexist, much as the human brain splits short-term and long-term memory:

  • HBM where ultra-fast compute is needed
  • HBF where vast knowledge has to be stored

The first HBF specification is now public. The next proof points are shipping HBF parts and an AI accelerator that uses them alongside HBM; until both arrive, HBF is a design target rather than a product you can buy.

Render of a tall memory stack beside a processor on a package substrate
Memory stack beside a processor. Image: Techqio

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